1. Field of the Invention
The present invention relates to a data processor, and more particularly to a data processor, such as a microprocessor, having a buffer memory (cache memory) which is based on a direct map scheme or set associative scheme and having the ability of fast partial clearing of the buffer memory.
2. Description of the Related Art
Partial clearing of a buffer memory is a process of invalidating an entry of the buffer memory when part of tag bits of the entry are coincident with a designated value. This process is used, for example, when part of entries of the address translation look aside buffer memory (address translation cache memory) mismatch with the entries of the address translation table as a result of rewriting of the address translation look aside table and these buffer entries need to be invalidated. If this partial clearing is not possible, all entries will have to be invalidated, resulting in a degraded hit rate.
When a buffer memory has an increased capacity, in which case the proportion of unmatched entries decreases relatively, an unnecessary clearing process associated with all-entry invalidation will increase. Therefore, in increasing the capacity of a buffer memory with a possibility of mismatching of part of entries, such as the address translation buffer and logical cache, it is necessary to provide the ability of partial clearing.
Conventionally, buffer memories based on the full associative scheme are capable of carrying out simultaneous tag comparison for all entries and accordingly fast partial clearing can take place, whereas buffer memories based on the direct map scheme or set associative scheme necessitate sequential reading of tags of entries for comparison, and time spent for partial clearing increases in proportion to the number of entries, i.e., the capacity of buffer memory.